1. Field of the Invention
The present invention relates to an output circuit, and more particularly to an output circuit which is connected to a semiconductor integrated circuit device having an external power supply voltage higher than an internal power supply voltage thereof and is appropriate for a signal interface of the semiconductor integrated circuit device.
2. Description of the Related Art
In general, since the scale of circuits which can be integrated in one semiconductor integrated circuit device is limited, a plurality of semiconductor integrated circuit devices constitute one system. In this case, however, there may be different power supply voltages in signal interfaces between the semiconductor integrated circuit devices.
For this reason, where semiconductor integrated circuit devices with different signal levels (for example, 3.3 V and 5V) are connected with each other, one of the semiconductor integrated circuit devices having a lower power supply voltage requires a signal interface corresponding to the signal level of the other semiconductor integrated circuit device having a higher power supply voltage.
In this case, it is common that the semiconductor integrated circuit device having the lower power supply voltage employs, as the signal interface, a tolerant output circuit capable of applying a higher external power supply voltage or performing a pull-up operation. Such output circuits are disclosed in, for example, Japanese Patent Nos. 3340906, 3366484 and 3432229.
In the '906 patent or '229 patent, an output circuit has three PMOS transistors formed in a floating well. When a high external potential is applied, the first and second PMOS transistors are turned off, so as to prevent the flow of external current resulting from the external potential to an internal power supply voltage.
In the output circuit of the '484 patent, even if a high power supply potential is applied from a different output driver circuit when an output terminal is in a high impedance state, the output circuit prevents the flow of current from the high power supply potential to a low power supply potential.
FIG. 2 of the accompanying drawings is a circuit diagram showing the configuration of a conventional output circuit for a semiconductor integrated circuit device, more particularly an output pull-up state buffer circuit 100.
In FIG. 2, a terminal EB receives a signal that enables/disables the circuit 100. When the EB input becomes ‘L’ in level (low level), an output node 32 of a 2-input NAND circuit 1 becomes ‘H’ in level (high level), thereby causing a PMOS transistor P9 to be turned off. Because an output node 14 of a 2-input NOR circuit 3 becomes ‘L’ in level, an NMOS transistor N9 is turned off, too. As a result, no signal is generated from an output terminal OUT. Consequently, the circuit 100 is disabled. On the other hand, when the EB input becomes ‘H’ in level, the circuit 100 is enabled and a signal corresponding to an input introduced to an input terminal IN is issued from the output terminal OUT.
In the enabled state of the circuit 100, when the IN input becomes ‘H’ in level, the PMOS transistor P9 is turned on and the NMOS transistor N9 is turned off, so a VDD potential (3.3V) is supplied from the output terminal OUT. In contrast, when the IN input becomes ‘L’ in level, the PMOS transistor P9 is turned off and the NMOS transistor N9 is turned on, so a ground potential is supplied from the output terminal OUT.
FIG. 4 of the accompanying drawings is a circuit diagram showing the configuration of a conventional output circuit 200 of an open drain type. In FIG. 4, an NMOS transistor N24 has a source connected to the drain of an NMOS transistor N25, a drain connected to an output terminal OUT and a gate connected to a power supply voltage VDD for output. Accordingly, the NMOS transistor N24 is configured to be normally on (always on). The NMOS transistor N25 has a gate connected to the output of an inverter 23, a source connected to a ground voltage GND and a drain connected to the source of the NMOS transistor N24. In the output circuit 200 of the open drain type of FIG. 4, the output signal has an amplitude between 0V and an external power supply voltage VTT (for example, 5V).
FIG. 3 of the accompanying drawings shows variations in respective potentials of the input terminal IN, output terminal OUT and node 35 in the circuit 100 of FIG. 2 when the circuit 100 is in the enabled state.
In FIG. 2, the output terminal OUT is connected to the external power supply voltage VTT (5V) via a resistor 21. When the output voltage from the output terminal OUT is the ground potential, there is no problem: the output voltage from the output terminal OUT becomes substantially the same as the ground potential because the VTT voltage is dropped across the resistor 21.
However, when the output from the output terminal OUT is the VDD potential, the VTT voltage is also dropped across the resistor 21 so that the output from the output terminal OUT stops at about VDD (3.3V), i.e., the output does not reach VTT (5V). Accordingly, there is a possibility that a device connected to the OUT terminal does not normally operate.
In the output circuit 200 of FIG. 4, when the output terminal OUT is changed from an ‘L’ level to an ‘H’ level, it generates an ‘H’ level signal depending on the external power supply voltage, so that the relationship between VIH and VOH as described above is satisfied without complication. That is, the amplitude of the output signal from the output terminal OUT rises to the external voltage (for example, 5V).
However, as shown in FIG. 5 of the accompanying drawings, the voltage rising of the output terminal OUT from 0V to the external power supply voltage (5V) is delayed because the speed thereof is determined by an external resistor 22.